module beamforming_processor (
    input  wire        clk,
    input  wire        rst_n,
    input  wire        time_vld,
    input  wire [23:0] time_data [15:0],
    input  wire        freq_vld,
    input  wire [31:0] freq_real [15:0][127:0],
    input  wire [31:0] freq_imag [15:0][127:0],
    input  wire [8:0]  target_angle,
    input  wire [1:0]  algorithm_select,  // 算法选择
    
    // 波束成形输出
    output wire [23:0] beamformed_output,
    output wire        output_vld,
    output wire [3:0]  beam_state
);

// 算法模块实例化
delay_sum_beamformer u_delay_sum (
    .clk(clk),
    .rst_n(rst_n),
    .time_vld(time_vld),
    .time_data(time_data),
    .target_angle(target_angle),
    .beamformed_output(ds_output),
    .output_vld(ds_vld)
);

mvdr_beamformer u_mvdr (
    .clk(clk),
    .rst_n(rst_n),
    .freq_vld(freq_vld),
    .freq_real(freq_real),
    .freq_imag(freq_imag),
    .target_angle(target_angle),
    .beamformed_output(mvdr_output),
    .output_vld(mvdr_vld)
);

// 算法选择器
algorithm_selector u_selector (
    .clk(clk),
    .rst_n(rst_n),
    .algorithm_select(algorithm_select),
    .ds_output(ds_output),
    .ds_vld(ds_vld),
    .mvdr_output(mvdr_output),
    .mvdr_vld(mvdr_vld),
    .final_output(beamformed_output),
    .final_vld(output_vld)
);

endmodule